1. Field
The present invention relates to a semiconductor memory having memory cells of DRAM and an interface of SRAM.
2. Description of the Related Art
A pseudo SRAM has memory cells of DRAM (dynamic memory cells) and operates as SRAM by internally and automatically executing a refresh operation of memory cells. The pseudo SRAM executes the refresh operation without being recognized by a controller such as CPU, during a period in which a read operation or a write operation of a memory core is not executed. The refresh operation is executed in response to an internal refresh request which occurs periodically inside the pseudo SRAM.
When the internal refresh request conflict with an external access request, the refresh operation is executed with higher priority than an access operation (read operation or write operation). At this time, to make it possible to insert the refresh operation during an access cycle, an access cycle time, which is a minimum supply interval for an access command (read command or write command), is set to a time obtained by adding a refresh operation time of the memory core to a read operation time or a write operation time of the memory core.
An effective value of a read access time from supplying of a read command to outputting of read data, and an effective value of a write access time from supplying of a write command to writing of write data to a memory cell becomes worst when the refresh operation is inserted. In a test of the pseudo SRAM, it is necessary to evaluate a worst access time. Since the generation period of the internal refresh request is much longer than that of the access cycle time, it is difficult to insert the refresh operation during an access cycle efficiently to evaluate the worst access time. Accordingly, there is proposed a technique in which a test mode is provided in the pseudo SRAM, and a refresh request is generated forcibly in synchronization with an access command during the test mode (for example, Japanese Unexamined Patent Application Publication No. 2005-92978). Also, there is proposed a technique in which a refresh operation is executed just before or after an access operation in response to an internal refresh request or an externally supplied trigger signal (for example, Japanese Unexamined Patent Application Publication No. 2006-59489).
Conventionally, a refresh operation during the test mode is always executed together with an access operation in response to an access request. Since the refresh operation that is normally unnecessary is performed, the access cycle time cannot be shortened, thereby resulting in poor test efficiency.